EP1C12Q240C8 Introduction
The Cyclone® field programmable gate array family is based on a 1.5-V,0.13-μm, all-layer copper SRAM process, with densities up to20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features likephase-locked loops (PLLs) for clocking and a dedicated double data rate(DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM)memory requirements, Cyclone devices are a cost-effective solution fordata-path applications. Cyclone devices support various I/O standards,including LVDS at data rates up to 640 megabits per second (Mbps), and66- and 33-MHz, 64- and 32-bit peripheral component interconnect (PCI),for interfacing with and supporting ASSP and ASIC devices. Altera alsooffers new low-cost serial configuration devices to configure Cyclonedevices.EP1C12Q240C8 FeaturesThe Cyclone device family offers the following features: ■ 2,910 to 20,060 LEs, see Table 1–1■ Up to 294,912 RAM bits (36,864 bytes)■ Supports configuration through low-cost serial configuration device■ Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards■ Support for 66- and 33-MHz, 64- and 32-bit PCI standard■ High-speed (640 Mbps) LVDS I/O support■ Low-speed (311 Mbps) LVDS I/O support■ 311-Mbps RSDS I/O support■ Up to two PLLs per device provide clock multiplication and phaseshifting■ Up to eight global clock lines with six clock resources available perlogic array block (LAB) row■ Support for external memory, including DDR SDRAM (133 MHz),FCRAM, and single data rate (SDR) SDRAM■ Support for multiple intellectual property (IP) cores, includingAltera® MegaCore® functions and Altera Megafunctions PartnersProgram (AMPPSM) megafunctions.