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產品介紹
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‧ High-density, High-performance, Electrically-erasable Complex Programmable
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Logic Device
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– 64 Macrocells
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– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
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– 44, 68, 84, 100 Pins
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– 7.5 ns Maximum Pin-to-pin Delay
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– Registered Operation up to 125 MHz
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– Enhanced Routing Resources
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‧ In-System Programmability (ISP) via JTAG
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‧ Flexible Logic Macrocell
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– D/T/Latch Configurable Flip-flops
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– Global and Individual Register Control Signals
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– Global and Individual Output Enable
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– Programmable Output Slew Rate
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– Programmable Output Open Collector Option
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– Maximum Logic Utilization by Burying a Register with a COM Output
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‧ Advanced Power Management Features
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– Automatic μA Standby for “L” Version
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– Pin-controlled 1 mA Standby Mode
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– Programmable Pin-keeper Circuits on Inputs and I/Os
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– Reduced-power Feature per Macrocell
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‧ Available in Commercial and Industrial Temperature Ranges
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‧ Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
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‧ Advanced EE Technology
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– 100% Tested
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– Completely Reprogrammable
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– 10,000 Program/Erase Cycles
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– 20-year Data Retention
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– 2000V ESD Protection
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– 200 mA Latch-up Immunity
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‧ JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
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‧ PCI-compliant
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‧ 3.3V or 5.0V I/O Pins
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‧ Security Fuse Feature
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‧ Green (Pb/Halide-fee/RoHS Compliant) Package Options
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Datasheet： |
