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View All / Development Boards / FPGA / CPLD
XC95144XL-10TQG144C CPLD 144 Macrocells 3.3V TQFP-144

XC95144XL-10TQG144C CPLD 144 Macrocells 3.3V TQFP-144

3.3V high-performance CPLD for logic integration and high-speed control design
144 macrocells | 3,200 gates | 5ns | 178MHz | 144-pin TQFP with 117 I/O | JTAG / ISP
5V tolerant I/O accepts 5V / 3.3V / 2.5V, 10,000 program cycles, 20-year data retention
Also known as: XC95144

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NT$210
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Description
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Description

 

產品介紹

• 5 ns pin-to-pin logic delays

• System frequency up to 178 MHz

• 144 macrocells with 3,200 usable gates

• Available in small footprint packages

- 100-pin TQFP (81 user I/O pins)

- 144-pin TQFP (117 user I/O pins)

- 144-CSP (117 user I/O pins)

- Pb-free available for all packages

• Optimized for high-performance 3.3V systems

- Low power operation

- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

- 3.3V or 2.5V output capability

- Advanced 0.35 micron feature size CMOS Fast FLASH™ technology

• Advanced system features

- In-system programmable

- Superior pin-locking and routability with Fast CONNECT™ II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with individual product-term allocation

- Local clock inversion with three global and one product-term clocks

- Individual output enable per output pin with local inversion

- Input hysteresis on all user and boundary-scan pin inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase cycles

- 20 year data retention

- ESD protection exceeding 2,000V

• Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package
 

WARNING: Programming temperature range of

TA = 0° C to +70° C

 
 
Datasheet：

 

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