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XC95144XL-10TQG144C CPLD 可程式邏輯元件 144 巨集單元 3.3V TQFP-144

XC95144XL-10TQG144C CPLD 可程式邏輯元件 144 巨集單元 3.3V TQFP-144

3.3V 高效能 CPLD,適合邏輯整合與高速控制設計
144 Macrocell|3,200 閘|5ns|178MHz|144-pin TQFP 117 I/O|JTAG/ISP
I/O 相容 5V/3.3V/2.5V,抹寫 10,000 次、資料保存 20 年


全店,滿千免運優惠(限郵寄和超商純取貨)

全店,本賣場無實體店面,無提供自取服務,敬請見諒。

NT$210
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商品描述
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商品描述

 

產品介紹

• 5 ns pin-to-pin logic delays

• System frequency up to 178 MHz

• 144 macrocells with 3,200 usable gates

• Available in small footprint packages

- 100-pin TQFP (81 user I/O pins)

- 144-pin TQFP (117 user I/O pins)

- 144-CSP (117 user I/O pins)

- Pb-free available for all packages

• Optimized for high-performance 3.3V systems

- Low power operation

- 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals

- 3.3V or 2.5V output capability

- Advanced 0.35 micron feature size CMOS Fast FLASH™ technology

• Advanced system features

- In-system programmable

- Superior pin-locking and routability with Fast CONNECT™ II switch matrix

- Extra wide 54-input Function Blocks

- Up to 90 product-terms per macrocell with individual product-term allocation

- Local clock inversion with three global and one product-term clocks

- Individual output enable per output pin with local inversion

- Input hysteresis on all user and boundary-scan pin inputs

- Bus-hold circuitry on all user pin inputs

- Full IEEE Standard 1149.1 boundary-scan (JTAG)

• Fast concurrent programming

• Slew rate control on individual outputs

• Enhanced data security features

• Excellent quality and reliability

- Endurance exceeding 10,000 program/erase cycles

- 20 year data retention

- ESD protection exceeding 2,000V

• Pin-compatible with 5V-core XC95144 device in the 100-pin TQFP package

 

WARNING: Programming temperature range of

TA = 0° C to +70° C

 
 
Datasheet:

 

送貨及付款方式

送貨方式

  • 郵局國際貨運
  • 郵寄【請填寫收件地址】
  • 7-11 取貨付款 (C2C)
  • 7-11 取貨不付款 (C2C)
  • 黑貓-常溫
  • 黑貓-常溫(貨到付款)
  • 報價單草稿

付款方式

  • 專員接洽
  • Apple Pay
  • 銀行轉帳
  • 信用卡付款
  • 黑貓宅配(貨到付款)
  • 7-11取貨付款

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